Why modern out-of-order CPUs reorder memory operations at the hardware pipeline level:

CPUs use Store Buffers to delay writing data to L1 cache, allowing execution to proceed without waiting for cache line write confirmation. This can cause Store-Load reordering where a CPU reads a stale value before its prior write reaches other cores.

On x86, MFENCE or LOCK prefixed instructions flush the store buffer. On ARM, DMB ISH (Data Memory Barrier Inner Shareable) synchronizes load and store queues across all CPU clusters.

Hardware store buffers are the physical reason why multi-threaded memory models require atomic memory barriers.

Great low-level hardware breakdown.