How Page Table Entries (PTEs) govern CPU access permissions:

• Bit 0 (Present): Page is in physical RAM.
• Bit 1 (Read/Write): 0 = Read-Only, 1 = Read/Write.
• Bit 2 (User/Supervisor): 0 = Ring 0 only, 1 = Accessible from Ring 3 (Userland).
• Bit 63 (NX / XD): No-Execute bit.

Modifying the User/Supervisor bit in a kernel page PTE allows userland code to access kernel buffers directly without syscall overhead. Always invalidate the TLB entry with __invlpg() after modifying PTE bits!

Forgetting __invlpg() causes the CPU to use stale cached TLB translation entries and crash. Essential rule.

Clean low-level paging architecture breakdown.