Developer knowledge network ยท moderated exchange

UnreliableCode Community

Developer Research, Reverse Engineering & Coding Community

Knowledge indexLive
4Categories
919Threads
2.8KPosts
Tutorial

Implementing a Cache-Line Aligned Lock-Free SPSC Memory Queue in C++20 [v2.4 Technical Discussion]

ptr_arithmetic
C++ Wizard
MEMBER
Rep: 162
Join Date: May 2018
Posts: 73
Thanks: 42
1 months ago ยท Jun 28, 2026 4:07 AM
#1

To transfer game state coordinates from a background memory reader thread to an ImGui DirectX render thread with zero lock contention:

CPP
template<typename T, size_t Capacity>
class LockFreeSPSCQueue {
    static_assert((Capacity & (Capacity - 1)) == 0, "Capacity must be a power of 2");
    alignas(64) std::atomic<size_t> m_head{0};
    alignas(64) std::atomic<size_t> m_tail{0};
    alignas(64) T m_buffer[Capacity];
public:
    bool Push(const T& item) {
        size_t head = m_head.load(std::memory_order_relaxed);
        if (head - m_tail.load(std::memory_order_acquire) == Capacity) return false;
        m_buffer[head & (Capacity - 1)] = item;
        m_head.store(head + 1, std::memory_order_release);
        return true;
    }
    bool Pop(T& outItem) {
        size_t tail = m_tail.load(std::memory_order_relaxed);
        if (tail == m_head.load(std::memory_order_acquire)) return false;
        outItem = m_buffer[tail & (Capacity - 1)];
        m_tail.store(tail + 1, std::memory_order_release);
        return true;
    }
};

alignas(64) completely prevents CPU L1/L2 cache false sharing across CPU cores!

x64_assembler
Assembly Guru
MEMBER
Rep: 99
Join Date: Sep 2022
Posts: 14
Thanks: 16
1 months ago ยท Jun 28, 2026 7:54 AM
#2

Memory orders (memory_order_acquire / release) compile to zero extra barrier instructions on x86_64 while guaranteeing sequential consistency. Pure speed.

vtable_slayer
Senior Reverser
MEMBER
Rep: 215
Join Date: Mar 2018
Posts: 86
Thanks: 61
1 months ago ยท Jun 28, 2026 10:29 PM
#3

Processes 10,000,000 entity state pushes per second without a single mutex lock.