False sharing occurs when two independent threads modify variables that reside on the exact same 64-byte CPU cache line. Even though the variables are distinct, the hardware cache coherence protocol constantly invalidates cache lines across cores.

Use alignas(std::hardware_destructive_interference_size) on multi-threaded shared counters or per-thread state structures to ensure they occupy separate cache lines.

Adding proper alignment padding increased our parallel worker queue throughput by over 400% on a 16-core CPU!